1. Field of the Invention
Embodiments of the invention relate generally to the field of memory devices and more particularly, to techniques for accessing one or more protected modes of operation in serial peripheral interface-based NAND memory devices.
2. Description of the Related Art
A serial peripheral interface (SPI) is a communication interface standard that provides a synchronous serial data link between a master device and a slave device. For instance, an SPI interface may provide support for a low to medium bandwidth network connection amongst processors and other devices.
An SPI bus includes four wires including two control lines and two data lines. The two control lines include a Serial Clock (SCLK) line and a Chip Select (CS) line. The SCLK signal is used to clock the shifting of serial data simultaneously into and out of the master and slave devices, thereby allowing the SPI architecture to operate as a full duplex protocol. The CS line is driven with a signal that enables or disables the slave device being controlled by the master device. It is also possible for the master device to communicate with multiple slave devices, although each additional slave device may require an additional CS line.
The two data lines of the SPI bus include a Serial Data Out (SOUT) line and a Serial Data In (SIN) line. The SOUT line is a data communication line that is generally configured to transfer data from an output of the slave device to an input of the master device. Accordingly, in the unlikely scenario that a user attempts to drive input data on the SOUT line, the data is ignored by the device. Similarly, the SIN line is a data communication line configured to transfer data from the output of the master device to the input of the slave device. Typically, the SOUT and SIN lines are active when the CS signal received by the slave device transitions to an enabling state, such as active low or active high.
Because SPI utilizes only four lines of communication, SPI has become increasingly advantageous for use in systems and applications desiring compact and simple integrated circuit designs. Particularly, the SPI interface's relatively simple configuration of control and data lines allows for a relatively high board density at a low cost. For instance, the implementation of an SPI interface in a NAND-based flash memory may allow for integrated circuit designs having as few as 8 pins, whereas conventional devices may require 32 or more pins. Thus, SPI is ideal for providing a simple and easily compatible interface to more complex circuits, such a parallel NAND memory device.
Electronic devices, such as memory devices, are typically manufactured to include one or more “protected modes” of operation. These protected modes of operation may include access to certain features, commands, or registers in the device which are generally inaccessible in a “normal mode,” such as that which is typically available to an end-user consumer. For instance, a protected mode of operation may include a debug mode allowing authorized service technicians to determine a root cause of failure in the event of a defective device. Protected modes may also include a programming mode for setting various electronic trimmers and regulators on the device in accordance with a customer's design specifications, and a testing or evaluation mode for benchmarking or stress testing a device to determine the limits of its performance.
Although specific examples have been provided herein, it should be understood that a protected mode may be any mode of operation other than a normal mode. Further, because the aforementioned protected modes may include access to certain protected commands or registers capable of altering sensitive data or parameters of a device, such as firmware, trimmers, or regulators, improper tampering with protected mode functions, whether intentional or accidental, may result in undesirable performance or even damage to a device. Thus, it is often necessary to restrict access to protected modes to only authorized users, such as service technicians, engineers, designers, and so forth. Typically, this has been accomplished by requiring a protected mode entry sequence to be entered on a device, for example, on an input pin. The entry sequence may essentially include a plurality of commands which must be entered in a specific order so that protected mode access is permitted. However, without additional security or protective measures, the possibly exists that the protected mode entry sequence may be accidentally entered through software data entries occurring during a normal mode operation. The possibility also exists that an unauthorized user having gained knowledge of the entry sequence may access to the protected modes. Thus, current methods may not fully protect a device against accidental or intentional access to protected modes of operation by unauthorized users.
Embodiments of the present invention may be directed towards one or more of the problems set forth above.